1. Technical Field
The present invention relates to a reference cell layout.
The invention particularly, but not exclusively, relates to a reference cell layout for a memory device of the Flash type and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, a memory device, in particular of the Flash type, comprises an array of cells used to generate the reference currents for reading and verify operations of the memory device itself. These cells are usually indicated as reference cells.
It is also known that the commonly used reference cell layouts are normally designed like the memory cell ones. In this way, a good matching between reference and memory cells to be read is easily obtained.
More particularly, in the widely used CMOS technology, the active area scaling and the consequent reduction of the gate capacitance of the cells causes a worsening of Random Telegraph Noise or RTN immunity, due to the reduction of the total charge involved in threshold voltage determination, as described for instance in the article to Renesas Technology Corporation entitled: ‘The Impact of Random Telegraph Signal on the Scaling of Multilevel Flash Memories’, 2006 Symposium on VLSI circuit.
This charge reduction causes a fluctuation in the threshold voltage of the cells and consequently it could compromise the repeatability of the reading operations which substantially are threshold voltage readings.
The impact of the RTN is particularly critical for the reference cells since they are involved at each reading and verify operation of the memory device. Consequently, the threshold voltage indetermination induces a reduction of the reading margins of the memory device as a whole.
In particular, a “noise” affecting the measure of memory cells and compromising the repeatability of read information is not acceptable for any reliable memory device.
Moreover, along with the cells size scaling, a correct definition of small arrays, as in the case of the known reference cells, becomes more and more critical and requires challenging technology and design solutions.